This course aims to enable participants to design, verify or debug CHI-based IPs or interconnects. Participants get a detailed understanding of the CHI layered protocol. In order to explain the purpose of particular AXI signals, an introduction to TrustZone, exclusive resource management and MPU/MMU page attributes is provided. The attendees will learn about AXI ordering rules, that are required to understand the operation of an interconnect. They will also study cache hardware coherency through AMBA5-CHI protocol as well as stashing mechanism.
- Familiarity with Cortex ARM CPUs
- Knowledge of MMU and caches operation is recommended.
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
|Day 1||Day 2||Day 3|
|INTRODUCTION (1-hour)||INTRODUCTION TO CACHE AND TLB COHERENCY (1-hour)||PROTOCOL LAYER (3-hour)|
|TRUSTZONE ARCHITECTURE (1-hour)||EXCLUSIVE RESOURCE MANAGEMENT (2-hour)||QUALITY OF SERVICE (1-hour)|
|CACHE COHERENCY (4-hour)||LINK LAYER (2-hour)||ERROR HANDLING (2-hour)|
|CACHE STASHING (1-hour)||NETWORK LAYER (2-hour)||POWER MANAGEMENT (1-hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.