This course aims to enable participants to design, verify or debug AHB-based IPs or interconnects. Participants get a detailed understanding of the AHB-5 and APB-4 protocols. In order to explain the purpose of particular AHB signals, an introduction to TrustZone, exclusive resource management and MPU/MMU page attributes is provided. The attendees will learn about AHB ordering rules, that are required to understand the operation of an interconnect.
- Familiarity with Cortex ARM CPUs
- Knowledge of MMU and caches operation is recommended
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs or IPs based on ARM AMBA AHB5 and APB4 buses.
|Day 1||Day 2|
|INTRODUCTION TO AMBA SPECIFICATIONS (1 hour)||AHB5 PROTOCOL (6 hours)|
|TRUSTZONE ARCHITECTURE (2 hours)||APB4 PROTOCOL (1 hour)|
|EXCLUSIVE RESOURCE MANAGEMENT, SOFTWARE ASPECTS (2 hours)|
|MPU / MMU PAGE TYPES (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.