This course aims to explain the architecture of the ARM Cortex-A8 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the AArch32 V7-A specification. They will study the complex mechanisms specific to ARM V7-A processors, particularly TrustZone and MMU.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-A8 architecture.
|Day 1||Day 2||Day 3||Day 4|
|ARM BASICS (2 hours)||PAGE ATTRIBUTES (2 hours)||INTEGRATED L2 CACHE (2 hours)||CORESIGHT DEBUG (1 hour)|
|CORTEX-A8 ARCHITECTURE (1 hour)||MEMORY MANAGEMENT UNIT (3 hours)||EXCLUSIVE RESOURCE MANAGEMENT (2 hours)||V7-A INSTRUCTION SET SUMMARY (2 hours)|
|HARDWARE IMPLEMENTATION (1 hour)||L1 CACHES (2 hours)||VIC AND LOW POWER MODES (2 hours)||FLOATING-POINT UNIT (1 hour)|
|INSTRUCTION PIPELINE (1 hour)||CORESIGHT DEBUG (1 hour)||EMBEDDED SOFTWARE DEVELOPMENT (3 hours)|
|TRUSTZONE (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A8: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode. This CSP is an ideal starting point for developing engineering test software, verification software, and proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set