This course aims to explain the architecture of the ARM Cortex-A32 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the AArch32 V8-A specification. They will study the complex mechanisms specific to ARM V8-A processors, particularly virtualization, TrustZone and MMU.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-A32 architecture.
|Day 1||Day 2||Day 3||Day 4|
|CORTEX-A32 ARCHITECTURE (2 hours)||TRUSTZONE (2 hours)||MEMORY MANAGEMENT UNIT- AARCH32 LPAE (1 hour)||A32 INSTRUCTION SET SUMMARY (1-hour)|
|HARDWARE IMPLEMENTATION (2 hours)||PAGE ATTRIBUTES (2 hours)||SYSTEM MMU, MMU500 (1 hour)||GICv4 AND LOW POWER MODES (2-hour)|
|INSTRUCTION PIPELINE (1 hour)||MEMORY MANAGEMENT UNIT - AARCH32 SHORT DESCRIPTORS (2 hours)||L1 AND L2 CACHES (2 hours)||CORESIGHT DEBUG (2-hour)|
|INTRODUCTION TO ARM ARCHITECTURE V8- AARCH32 (2 hours)||VIRTUALIZATION EXTENSIONS (1 hour)||HARDWARE CACHE COHERENCY (1 hour)||PERFORMANCE MONITOR (1-hour)|
|EXCLUSIVE RESOURCE MANAGEMENT (1 hour)||CRYPTOGRAPHY ENGINE (1-hour)|
|GENERIC TIMER (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A32: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode. This CSP is an ideal starting point for developing engineering test software, verification software, and proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set