This course aims to explain the architecture of the ARM Cortex-R52 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the V8-R specification. They will study the mechanisms specific to ARM V8-R processors, particularly caches, TCMs and MPU. Labs contribute to become familiar with V8-R programming.
Basic knowledge of a CPU or DSP
Duration & Attendance
- 4 days, 7 hours a day
- Min/max number of participants: 3-15
- On-site/intra (private session)
- Contact us for public sessions
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecture.
|Day 1||Day 2||Day 3||Day 4|
|ARM BASICS (2-hours)||HARDWARE IMPLEMENTATION (1-hour)||PAGE ATTRIBUTES (1-hour)||CORESIGHT DEBUG (2-hours)|
|CORTEX-R52 ARCHITECTURE (2-hours)||SAFETY FEATURES (1-hour)||MEMORY PROTECTION UNIT (1-hour)||V8-R INSTRUCTION SET SUMMARY (2-hours)|
|INTRODUCTION TO VIRTUALIZATION (2–hours)||INSTRUCTION PIPELINE (1-hour)||SYSTEM MMU, MMU500 (1-hour)||FLOATING-POINT UNIT (1-hour)|
|V8-R VIRTUALIZATION EXTENSIONS (1-hour)||GICv3 (3-hours)||CACHES AND TCMS (2-hours)||EMBEDDED SOFTWARE DEVELOPMENT (2-hours)|
|GENERIC TIMER (1-hour)||EXCLUSIVE RESOURCE MANAGEMENT (2-hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.