PCI EXPRESS GEN3 & GEN4 Training

Prerequesites and related courses: 
  • Experience of a digital bus is mandatory
Course objectives: 
  • This course covers the PCI Express Gen3 and Gen4 specifications
  • It does not describe the physical layer of PCI Express Gen1 and Gen2, see course CVT_PCIe2
  • It also handles latests specifications, such as SR-IOV and L1 Power Management sub-states
  • The course fully describes the PHY layer and explains how to qualify the analog part
  • All features related to power management are detailed
  • The course provides guidelines to perform software performance tuning
  • The new mechanisms used to implement cache coherency through a PCIe fabric are explained
Duration: 
5 Days
Program: 
DAY 1
  • INTRODUCTION TO PCI EXPRESS
  • SUMMARY OF PCIE GEN1 AND GEN2 PHYSICAL LAYER
  • THE PHYSICAL LAYER – GEN3 AND GEN4- LOGICAL SUB-BLOCK
DAY 2
  • THE PHYSICAL LAYER – GEN3 AND GEN4 ANALOG SUB-BLOCK
  • TESTING A PCI EXPRESS SYSTEM
  • POWER MANAGEMENT
  • HOT PLUG
DAY 3
  • PIPE INTERFACE
  • PACKET ROUTING
  • TLP ACKNOWLEDGEMENT
  • QUALITY OF SERVICE
  • FLOW CONTROL
DAY 4
  • TRANSACTION ORDERING
  • PACKET FORMAT
  • INTERRUPT MANAGEMENT
  • ERROR MANAGEMENT
  • THE CONFIGURATION SPACE
DAY 5
  • PROCESS ADDRESS SPACE ID (PASID)
  • SR-IOV
  • CACHE MANAGEMENT
  • PROTOCOL MULTIPLEXING
  • PRECISION TIME MEASUREMENT