• Call us:
  • +33 428 380 485
NXP e200Z4

NXP e200Z4

Course Family:
Freescale Power 32-bit Architecture
SKU/Ref:
NXP_E200Z4

Course Objectives

This course aims to explain the architecture of the e200z4 CPU to enable participants to efficiently design software. Attendees will get a detailed understanding of the internal architecture, especially the pipeline , exception mechanism, cache and CMPU. They will study the low level programming: assembler, C, EABI.

General Information

Prerequisites

Experience with a 32-bit processor or DSP is mandatory

Duration & Attendance

  • 3 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop software for e200z4 CPU.

Program Overview

Day 1 Day 2 Day 3
OVERVIEW (1 hour) DATA AND INSTRUCTION PATHS (1 hour) ASSEMBLER PROGRAMMING (2 hours)
INSTRUCTION PIPELINE (1 hour) L1 INSTRUCTION CACHE (2 hours) EABI (1 hour)
EXCEPTION MECHANISM (2 hours) DEBUG (3 hours) SIGNAL PROCESSING ENGINE (SPE) (3 hours)
MEMORY PROTECTION UNIT (3 hours) CLOCKING AND POWER MANAGEMENT (1 hour) VARIABLE LENGTH ENCODING (1 hour)

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of code sequences, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the e200z4: implements exceptions, cache, CMPU, access to special registers. This CSP is an ideal starting point for developing proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP

Optimized FFT: software implementation of a fixed point/floating point FFT using the SPE SIMD instruction set

Contact us to Learn More