This course aims to explain the architecture of the e200z4 CPU to enable participants to efficiently design software. Attendees will get a detailed understanding of the internal architecture, especially the pipeline , exception mechanism, cache and CMPU. They will study the low level programming: assembler, C, EABI.
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software for e200z4 CPU.
|Day 1||Day 2||Day 3|
|OVERVIEW (1 hour)||DATA AND INSTRUCTION PATHS (1 hour)||ASSEMBLER PROGRAMMING (2 hours)|
|INSTRUCTION PIPELINE (1 hour)||L1 INSTRUCTION CACHE (2 hours)||EABI (1 hour)|
|EXCEPTION MECHANISM (2 hours)||DEBUG (3 hours)||SIGNAL PROCESSING ENGINE (SPE) (3 hours)|
|MEMORY PROTECTION UNIT (3 hours)||CLOCKING AND POWER MANAGEMENT (1 hour)||VARIABLE LENGTH ENCODING (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e200z4: implements exceptions, cache, CMPU, access to special registers. This CSP is an ideal starting point for developing proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP
Optimized FFT: software implementation of a fixed point/floating point FFT using the SPE SIMD instruction set