This course aims to explain the architecture of the NXP e500mc PowerPC CPU to enable participants to efficiently develop low level software for P2041, P3 and P4 QorIQ SoCs. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the EREF specification. They will study the complex mechanisms specific to PowerPC processors, particularly pipeline, cache and MMU.
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software based on e500mc CPU.
|Day 1||Day 2||Day 3|
|OVERVIEW (1 hour)||EXCEPTION MECHANISM (2 hours)||HARDWARE CACHE COHERENCY (1 hour)|
|HYPERVISOR STATE AND PLATFORM VIRTUALIZATION (2 hours)||MEMORY MANAGEMENT UNIT (3 hours)||DEBUG (1 hour)|
|INSTRUCTION PIPELINE (3 hours)||L1 CACHES (1 hour)||CLOCKING AND POWER MANAGEMENT (1 hour)|
|DATA AND INSTRUCTION PATHS (1 hour)||L2 CACHE (1 hour)||ASSEMBLER PROGRAMMING (2 hours)|
|EABI (1 hour)|
|FLOATING-POINT UNIT (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e500mc: implements exceptions, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.