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NXP e5500

NXP e5500

Course Family:
Freescale Power 64-bit Architecture
SKU/Ref:
NXP_E5500

Course Objectives

This course aims to explain the architecture of the NXP e5500 PowerPC CPU to enable participants to efficiently develop low level software for P5 and T1 QorIQ SoCs. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the PowerPC 64-bit specification. They will study the complex mechanisms specific to PowerPC processors, particularly pipeline, cache and MMU.

General Information

Prerequisites

Experience with a 32 bit processor or DSP is mandatory

Duration & Attendance

  • 3 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop software based on e5500 CPU.

Program Overview

Day 1 Day 2 Day 3
OVERVIEW (1/2 hour) EXCEPTION MECHANISM (2 hours) HARDWARE CACHE COHERENCY (1 hour)
COMPUTATION MODES (1/2 hour) MEMORY MANAGEMENT UNIT (3 hours) DEBUG (1 hour)
HYPERVISOR STATE AND PLATFORM VIRTUALIZATION (2 hours) L1 CACHES (1 hour) CLOCKING AND POWER MANAGEMENT (1 hour)
INSTRUCTION PIPELINE (2 hours) L2 CACHE (1 hour) ASSEMBLER PROGRAMMING (2 hours)
DATA AND INSTRUCTION PATHS (2 hours)   EABI (1 hour)
    FLOATING-POINT UNIT (1 hour)

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of code sequences, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the e5500: implements exceptions, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode. 

Contact us to Learn More