This course aims to explain the architecture of the NXP e6500 PowerPC CPU to enable participants to efficiently develop low level software for P5 and T1 QorIQ SoCs. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the PowerPC 64-bit specification. They will study the complex mechanisms specific to PowerPC processors, particularly multi-threading, pipeline, cache and MMU.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software based on e6500 cluster.
|Day 1||Day 2||Day 3||Day 4|
|OVERVIEW (1/2 hour)||DATA AND INSTRUCTION PATHS (2 hours)||L1 CACHES (1 hour)||EABI (1 hour)|
|COMPUTATION MODES (1 hour)||EXCEPTION MECHANISM (2 hours)||CLUSTER L2 CACHE (1 hour)||FLOATING-POINT UNIT (2 hours)|
|HYPERVISOR STATE AND PLATFORM VIRTUALIZATION (2 hours)||MEMORY MANAGEMENT UNIT (3 hours)||HARDWARE CACHE COHERENCY (1 hour)||VECTOR UNITS (ALTIVEC) (4 hours)|
|MULTI-THREADING (1 hour)||DEBUG (2 hours)|
|INSTRUCTION PIPELINE (2 ½ -hours)||CORE AND CLUSTER POWER MANAGEMENT (1 hour)|
|ASSEMBLER PROGRAMMING (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e6500: implements exceptions, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
Optimized FFT: software implementation of a fixed point/floating point FFT using the Altivec SIMD instruction set