This course aims to enable participants to design, verify or debug PCIe gen1/2 IPs and links. Participants get a detailed understanding of the PCIe protocol. The attendees will learn about PCIe hardware and software implementation. Latest specifications, such as SR-IOV and L1 Power Management sub-states will be studied.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop systems based on PCIe gen1 and gen2.
|Day 1||Day 2||Day 3||Day 4|
|INTRODUCTION TO PCI EXPRESS (2 hours)||POWER MANAGEMENT (2 hours)||QUALITY OF SERVICE (1 hour)||HOT PLUG (1 hour)|
|THE PHYSICAL LAYER – GEN2- LOGICAL SUB-BLOCK (3 hours)||PIPE INTERFACE (2 hours)||FLOW CONTROL (1 hour)||THE CONFIGURATION SPACE (2 hours)|
|THE PHYSICAL LAYER – GEN2- ANALOG SUB-BLOCK (2 hours)||PACKET ROUTING (2 hours)||TRANSACTION ORDERING (1 hour)||SR-IOV (3 hours)|
|TLP ACKNOWLEDGEMENT (1 hour)||PACKET FORMAT (1 hour)||TESTING A PCI EXPRESS SYSTEM (1 hour)|
|INTERRUPT MANAGEMENT (2 hours)|
|ERROR MANAGEMENT (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.