Course Objectives
This course aims to enable participants to design, verify or debug UHS-II IPs and links. Participants get a detailed understanding of the UHS-II protocol, including half duplex and multi-lane operation. The attendees will learn how SD command are transported over the UHS II link. The enumeration and configuration for a point-to-point or ring topology will be studied.
General Information
Prerequisites
Familiarity with SD/MMC is recommended
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Location
On site/intra
Target Audience
Engineers and technicians who develop systems based on UHS-II.
Program Overview
| Day 1 | Day 2 |
|---|---|
| OVERVIEW OF UHS II (1 hour) | COMMON TRANSACTION LAYER (CM-TRAN) (2 hours) |
| PHYSICAL LAYER (2 hours) | SD TRANSACTION LAYER(SD-TRAN) (2 hours) |
| LINK LAYER (4 hours) | 2-LANE - HALF DUPLEX (2L-HD) (1 hour) |
| ADDITIONAL LANES SUPPORT (1 hour) | |
| PHY-LINK INTERFACE (1 hour) |
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Additional Information
Teaching Methods & Tools
Lectures with supporting slides, use of projector
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Trainees will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided
