This course aims to enable participants to design, verify or debug DDR3 memories and DDR3 controller IPs. Attendees will get a detailed understanding of the DDR3 Jedec standard. They will learn the protocol used to access DDR3 devices and will study the operation of the NXP i.MX6 DDR3 controller as an example of implementation.
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop or use SoCs supporting a DDR3 controller.
|Day 1||Day 2|
|INTRODUCTION TO DRAM (1 hour)||ELECTRICAL CHARACTERISTICS (3 hours)|
|DDR3 PACKAGE BALLOUT & ADDRESSING (1 hour)||iMX6 DDR3 CONTROLLER (MMDC) – DIGITAL PART (2 hours)|
|FUNCTIONAL DESCRIPTION (2 hours)||iMX6 DDR3 CONTROLLER (MMDC) – ANALOG PART (2 hours)|
|DDR3 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)|
|ON-DIE TERMINATION (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
PLDA has developed a LPDDR2 / DDR3 calibration firmware for NXP i.MX6 SoCs that dynamically adjusts the calibration values in less than 3 ms