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DDR4 SDRAM

DDR4 SDRAM

Course Family:
DDR and LPDDR
SKU/Ref:
DR_DDR4

Course Objectives

This course aims to enable participants to design, verify or debug DDR4 memories and DDR4 controller IPs. Attendees will get a detailed understanding of the DDR4 Jedec standard. They will learn the protocol used to access DDR4 devices and will study the operation of the NXP T1040 DDR4 controller as an example of implementation.

General Information

Prerequisites

Familiarity with Synchronous DRAM is recommended

Duration & Attendance

  • 2 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop or use SoCs supporting a DDR4 controller.

Program Overview

Day 1 Day 2
INTRODUCTION TO DRAM (1 hour) ON-DIE TERMINATION (1 hour)
DDR4 NEW FEATURES (2 hours) ELECTRICAL CHARACTERISTICS (2 hours)
DDR4 PACKAGE PINOUT & ADDRESSING (1 hour) NXP T1040 DDR4 CONTROLLER – DIGITAL PART (3 hours)
FUNCTIONAL DESCRIPTION (1 hour) NXP T1040 DDR4 CONTROLLER – ANALOG PART (1 hour)
DDR4 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)  

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided