This course aims to enable participants to design, verify or debug LPDDR2 memories and LPDDR2 controller IPs. Attendees will get a detailed understanding of the LPDDR2 Jedec standard. They will learn the protocol used to access LPDDR2 devices and will study the operation of the NXP i.MX6 LPDDR2 controller as an example of implementation.
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop or use SoCs supporting a LPDDR2 controller.
|Day 1||Day 2|
|INTRODUCTION TO DRAM (2 hours)||ELECTRICAL CHARACTERISTICS (3 hours)|
|LPDDR2 PACKAGE BALLOUT & ADDRESSING (1 hour)||iMX6 LPDDR2 CONTROLLER (MMDC) – DIGITAL PART (2 hours)|
|FUNCTIONAL DESCRIPTION (2 hours)||iMX6 LPDDR2 CONTROLLER (MMDC) – ANALOG PART (2 hours)|
|LPDDR2 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
PLDA has developed a LPDDR2 / DDR3 calibration firmware for NXP i.MX6 SoCs that dynamically adjusts the calibration values in less than 3 ms