This course aims to enable participants to design, verify or debug LPDDR3 memories and LPDDR3 controller IPs. Attendees will get a detailed understanding of the LPDDR3 Jedec standard. They will learn the protocol used to access LPDDR3 devices and will study the operation of the NXP i.MX7 LPDDR3 controller as an example of implementation.
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop or use SoCs supporting a LPDDR3 controller.
|Day 1||Day 2|
|INTRODUCTION TO DRAM (2 hours)||ELECTRICAL CHARACTERISTICS (3 hours)|
|LPDDR3 PACKAGE BALLOUT & ADDRESSING (1 hour)||iMX7 LPDDR3 CONTROLLER – DIGITAL PART (2 hours)|
|FUNCTIONAL DESCRIPTION (2 hours)||iMX7 LPDDR3 CONTROLLER – ANALOG PART (2 hours)|
|LPDDR3 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.