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LPDDR3 SDRAM

LPDDR3 SDRAM

Course Family:
DDR and LPDDR
SKU/Ref:
DR_LPDDR3

Course Objectives

This course aims to enable participants to design, verify or debug LPDDR3 memories and LPDDR3 controller IPs. Attendees will get a detailed understanding of the LPDDR3 Jedec standard. They will learn the protocol used to access LPDDR3 devices and will study the operation of the NXP i.MX7 LPDDR3 controller as an example of implementation.

General Information

Prerequisites

Familiarity with Synchronous DRAM is recommended

Duration & Attendance

  • 2 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop or use SoCs supporting a LPDDR3 controller.

Program Overview

Day 1 Day 2
INTRODUCTION TO DRAM (2 hours) ELECTRICAL CHARACTERISTICS (3 hours)
LPDDR3 PACKAGE BALLOUT & ADDRESSING (1 hour) iMX7 LPDDR3 CONTROLLER – DIGITAL PART (2 hours)
FUNCTIONAL DESCRIPTION (2 hours) iMX7 LPDDR3 CONTROLLER – ANALOG PART (2 hours)
LPDDR3 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)  

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided