This course aims to enable participants to design, verify or debug LPDDR4 memories and LPDDR4 controller IPs. Attendees will get a detailed understanding of the LPDDR4 Jedec standard. They will learn the protocol used to access LPDDR4 devices and will study the operation of the NXP i.MX8 LPDDR4 controller as an example of implementation.
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop or use SoCs supporting a LPDDR4 controller.
|Day 1||Day 2|
|INTRODUCTION TO DRAM (1 hour)||ON DIE TERMINATION (ODT) FOR COMMAND/ADDRESS BUS (1-hour)|
|LPDDR4 NEW FEATURES (2 hours)||TRAINING PROCEDURES (3-hour)|
|LPDDR4 PACKAGE PINOUT & ADDRESSING (1 hour)||ELECTRICAL CHARACTERISTICS (1-hour)|
|FUNCTIONAL DESCRIPTION (1 hour)||iMX8 LPDDR4 CONTROLLER (2-hour)|
|LPDDR4 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.