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LPDDR4 SDRAM

LPDDR4 SDRAM

Course Family:
DDR and LPDDR
SKU/Ref:
DR_LPDDR4

Course Objectives

This course aims to enable participants to design, verify or debug LPDDR4 memories and LPDDR4 controller IPs. Attendees will get a detailed understanding of the LPDDR4 Jedec standard. They will learn the protocol used to access LPDDR4 devices and will study the operation of the NXP i.MX8 LPDDR4 controller as an example of implementation.

General Information

Prerequisites

Familiarity with Synchronous DRAM is recommended

Duration & Attendance

  • 2 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop or use SoCs supporting a LPDDR4 controller.

Program Overview

Day 1 Day 2
INTRODUCTION TO DRAM (1 hour) ON DIE TERMINATION (ODT) FOR COMMAND/ADDRESS BUS (1-hour)
LPDDR4 NEW FEATURES (2 hours) TRAINING PROCEDURES (3-hour)
LPDDR4 PACKAGE PINOUT & ADDRESSING (1 hour) ELECTRICAL CHARACTERISTICS (1-hour)
FUNCTIONAL DESCRIPTION (1 hour) iMX8 LPDDR4 CONTROLLER (2-hour)
LPDDR4 COMMAND DEFINITIONS AND TIMING DIAGRAMS (2 hours)  

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided