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NXP MPC5748G

NXP MPC5748G

Course Family:
NXP Automotive and Industrial MCUs
SKU/Ref:
NXP_MPC5748

Course Objectives

This course aims to explain the architecture of the MPC5748G SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including communication units and integrated safety mechanisms.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • The e200z4 CPU is covered by another course entitled NXP_E200Z4

Duration & Attendance

  • 4 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on MPC5748G.

Program Overview

Day 1 Day 2 Day 3 Day 4
ARCHITECTURE OF MPC5748G (1 hour) HARDWARE IMPLEMENTATION (3 hours) ANALOG MODULES (3 hours) ULTRA SECURED DIGITAL HOST CONTROLLER (uSDHC) (2 hours)
SAFETY MECHANISMS (1 hour) SYSTEM MODULES (4 hours) CALIBRATION AND DEBUG MODULES (4 hours) USB CONTROLLERS (1 hour)
CORE COMPLEX OVERVIEW (1 hour)     SYNCHRONOUS AUDIO INTERFACE (SAI) (1 hour)
EMBEDDED MEMORIES (2 hours)     ETHERNET MAC (ENET) (2 hours)
SECURITY (2 hours)     OTHER COMMUNICATION MODULES (1 hour)

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
• Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee fill fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the e200z4 and e200z2: implements exceptions, L1 cache, CMPU protection and supports multicore in AMP mode. This CSP is an ideal starting point for developing engineering test software, verification software, and proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP

SoC Software Package (SSP) for the MPC8548G: implements drivers for interrupt controller, SMPU, eDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications

Contact us to Learn More

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