This course aims to explain the architecture of the MPC5777M SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including communication units and integrated safety mechanisms.
- Experience with a 32-bit processor or DSP is mandatory
- The e200z7 CPU is covered in course NXP_E200Z7
- The e200z4 CPU is covered in course NXP_E200Z4
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on MPC5777M.
|Day 1||Day 2||Day 3||Day 4|
|ARCHITECTURE OF MPC5777M (1 hour)||HARDWARE IMPLEMENTATION (3 hours)||ANALOG MODULES (3 hours)||COMMUNICATION MODULES (7 hours)|
|SAFETY MECHANISMS (2 hours)||SYSTEM MODULES (4 hours)||CALIBRATION AND DEBUG MODULES (4 hours)|
|CORE COMPLEX OVERVIEW (1 hour)|
|EMBEDDED MEMORIES (1 hour)|
|SECURITY (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e200z7 and e200z4: implements exceptions, L1 cache, CMPU protection and supports multicore in AMP mode. This CSP is an ideal starting point for developing engineering test software, verification software, and proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP
SoC Software Package (SSP) for the MPC5777M: implements drivers for interrupt controller, SMPU, eDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications