This course aims to explain the architecture of the NXP i.MX51 SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the multimedia units.
- Experience with a 32-bit processor or DSP is mandatory
- Note that the Cortex-A8 ARM CPU is covered by another course entitled ARM_A8
Duration & Attendance
- 5 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on i.MX51.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||SYSTEM RESET CONTROLLER (SRC) (2 hours)||ENHANCED SECURE DIGITAL HOST CONTROLLER (1 hour)||I2C CONTROLLER (1/2 hour)||SYNCHRONOUS SERIAL INTERFACE (SSI) (2 hours)|
|INTERCONNECT (1 hour)||UBOOT (1 hour)||USB CONTROLLERS (1 hour)||UART (1/2 hour)||DIGITAL AUDIO MULTIPLEXER (AUDMUX) (1 hour)|
|HARDWARE IMPLEMENTATION (1 hour)||ENHANCED SDRAM CONTROLLER (ESDCTL) (2 hours)||TIMERS (1/2 hour)||IMAGE PROCESSING UNIT (IPU) (3 hours)||SECURITY OVERVIEW (1 hour)|
|GENERAL POWER CONTROLLER (1 hour)||WIRELESS EXTERNAL INTERFACE MODULE (1 hour)||TRUSTZONE INTERRUPT CONTROLLER (TZIC) (1 hour)||GRAPHICAL PROCESSING UNITS (GPUs) (1 hour)||CENTRAL SECURITY UNIT (CSU) (1 hour)|
|IOMUX (1 hour)||NAND FLASH CONTROLLER (1 hour)||ETHERNET MAC (ENET) (1 hour)||VIDEO PROCESSING UNIT (VPU) (2 hours)||SYMMETRIC/ASYMMETRIC HASHING AND RANDOM ACCELERATOR (SAHARA) (2 hours)|
|CLOCK CONTROLLER MODULE (CCM) (2 hours)||SMART DMA (SDMA) (2 hours)|
|ENHANCED CONFIGURABLE SERIAL PERIPHERAL INTERFACE (eCSPI) (1/2 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A8: implements exceptions, GIC, L1 cache, L2 cache, MMU paging
SoC Software Package (SSP) for the NXP i.MX51: implements drivers for interrupt controller, SDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set