This course aims to explain the architecture of the NXP i.MX6DL/DP/QDP SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the multimedia units.
- Experience with a 32-bit processor or DSP is mandatory
- Note that the Cortex-A9 ARM CPU is covered by another course entitled ARM_A9
Duration & Attendance
- From 5 to 7 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on i.MX6DL/DP/DQP.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||SYSTEM RESET CONTROLLER (SRC) (2 hours)||GENERAL PURPOSE MEDIA INTERFACE (GPMI) (2 hours)||ETHERNET MAC (ENET) (2 hours)||MIPI D-PHY (1 hour)|
|INTERCONNECT (1 hour)||UBOOT (1 hour)||PCIE BRIDGE (2 hours)||USB CONTROLLERS (1 hour)||CAMERA SERIAL INTERFACE HOST CONTROLLER (MIPI_CSI) (1 hour)|
|HARDWARE IMPLEMENTATION (2 hours)||GENERAL POWER CONTROLLER (GPC) (1 hour)||ULTRA SECURED DIGITAL HOST CONTROLLER (uSDHC) (2 hours)||FLEXCAN CONTROLLERS (1 hour)||DISPLAY SERIAL INTERFACE (MIPI_DSI) (1 hour)|
|IOMUX (1 hour)||MULTI-MODE DDR CONTROLLER (MMDC) (2 hours)||SATA CONTROLLER- i.MX6DQ AND i.MXDQP (1 hour)||SMART DMA (SDMA) (1 hour)||IMAGE PROCESSING UNIT (IPU) (3 hours)|
|CLOCK CONTROLLER MODULE (CCM) (1 ½ hour)||EXTERNAL INTERFACE MODULE (EIM) (1 hour)||ENHANCED CONFIGURABLE SERIAL PERIPHERAL INTERFACE (eCSPI) (1 hour)||PIXEL PIPELINE – i.MX6DL (1 hour)|
|TIMERS (1/2 hour)||I2C CONTROLLER (1/2 hour)|
|UART (1/2 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A9: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and multicore in SMP or AMP mode
SoC Software Package (SSP) for the NXP i.MX6: implements drivers for interrupt controller, SDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications
LPDDR2 / DDR3 calibration firmware that dynamically adjusts the calibration values in less than 3 ms
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set