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NXP i.MX6SL

NXP i.MX6SL

Course Family:
NXP i.MX Application Processors
SKU/Ref:
NXP_IMX6SL

Course Objectives

This course aims to explain the architecture of the NXP i.MX6 Solo SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the multimedia units.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • Note that the Cortex-A9 ARM CPU is covered by another course entitled ARM_A9

Duration & Attendance

  • 5 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on i.MX6 Solo.

Program Overview

Day 1 Day 2 Day 3 Day 4 Day 5
OVERVIEW (1-hour) SYSTEM RESET CONTROLLER (SRC) (2 hours) ULTRA SECURED DIGITAL HOST CONTROLLER (uSDHC) (2 hours) I2C CONTROLLER (1/2 hour) SYNCHRONOUS SERIAL INTERFACE (SSI) (2 hours)
INTERCONNECT (1-hour) UBOOT (1 hour) FAST ETHERNET MAC (2 hours) UART (1/2 hour) DIGITAL AUDIO MULTIPLEXER (AUDMUX) (1 hour)
HARDWARE IMPLEMENTATION (2-hour) GENERAL POWER CONTROLLER (GPC) (1 hour) USB CONTROLLERS (1 hour) CAMERA SERIAL INTERFACE (1 hour) SECURITY OVERVIEW (1 hour)
IOMUX (1-hour) MULTI-MODE DDR CONTROLLER (MMDC) (2 hours) SMART DMA (SDMA) (1 hour) ENHANCED LCD INTERFACE (ELCDIF) (2 hours) CENTRAL SECURITY UNIT (CSU) (1/2 hour)
CLOCK CONTROLLER MODULE (CCM) (1 ½ -hour) EXTERNAL INTERFACE MODULE (EIM) (1 hour) ENHANCED CONFIGURABLE SERIAL PERIPHERAL INTERFACE (eCSPI) (1 hour) ELECTROPHORETIC DISPLAY CONTROLLER (EPDC) (1 hour) SECURE NON VOLATILE STORAGE (SNVS) (1 hour)
TIMERS (1/2-hour)     PIXEL PIPELINE (1 hour) RANDOM NUMBER GENERATOR (1/2-hour)
      GRAPHICAL PROCESSING UNIT 2D (1 hour) DATA CO-PROCESSOR (DCP) (1 hour)

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the ARM® Cortex™-A9: implements exceptions, GIC, L1 cache, L2 cache, MMU paging  and multicore in SMP or AMP mode

SoC Software Package (SSP) for the NXP i.MX6: implements drivers for interrupt controller, SDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications

LPDDR2 / DDR3 calibration firmware that dynamically adjusts the calibration values in less than 3 ms

Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set

Contact us to Learn More

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