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NXP LS1046A

NXP Layerscape LS1046A

Course Family:
NXP QorIQ Layerscape Processors
SKU/Ref:
NXP_LS1046

Course Objectives

This course aims to explain the architecture of the NXP LS1046A SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including network accelerators.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • Note that the Cortex-A72 ARM CPU is covered by another course entitled ARM_A72

Duration & Attendance

  • 5 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on LS1046A.

Program Overview

Day 1 Day 2 Day 3 Day 4 Day 5
OVERVIEW (1 hour) RUN CONTROL AND POWER MANAGEMENT (1 hour) ENHANCED SECURE DIGITAL HOST CONTROLLER (1 hour) DPAA OVERVIEW (2 hours) FRAME MANAGER (4 hours)
INTERCONNECT (1 hour) DDR4 CONTROLLER (2 hours) SATA CONTROLLER (1 hour) ETHERNET MACS (1 hour) SECURITY ENGINE (3 hours)
SYSTEM MMU, MMU500 (1 hour) INTEGRATED FLASH CONTROLLER (1 hour) ENHANCED DIRECT MEMORY ACCESS (eDMA) (1 hour) QUEUE MANAGER (3 hours)  
HARDWARE IMPLEMENTATION (1 hour) PCIE BRIDGE (2 hours) QUEUE DIRECT MEMORY ACCESS (qDMA) (1 hour) BUFFER MANAGER (1 hour)  
CLOCKING AND RESET (2 hours) QUAD SPI (1 hour) USB CONTROLLERS (1 hour)    
TRUST ARCHITECTURE (1 hour)   LOW SPEED SERIAL INTERFACES (1 hour)    
    FLEXTIMER MODULE (1 hour)    

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the ARM® Cortex™-A72: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.

SoC Software Package (SSP) for the NXP LS1046A: implements drivers for interrupt controller, memory controllers, uart and edma. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.

Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set

Contact us to Learn More

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