This course aims to explain the architecture of the NXP LS1088A SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including network accelerators.
Experience with a 32-bit processor or DSP is mandatory
Duration & Attendance
- From 5 to 7 days, 7 hours a day
- Min/max number of participants: 3 - 15
- On-site/intra (private session)
- Contact us for public sessions
Engineers and technicians who develop boards and software based on LS1088A.
|Day 1||Day 2||Day 3||Day 4||Day 5||Day 6||Day 7|
|OVERVIEW (1-hour)||TRUST ARCHITECTURE (1-hour)||QUAD SPI (1-hour)||DPAA2 OVERVIEW (2-hours)||WRIOP CLASSIFIER AND TABLE LOOKUP UNIT (WRIOP-CTLU) (2-hours)||MACSEC (2-hours)||QUICC ENGINE - SYSTEM INTERFACE (1-hour)|
|INTERCONNECT (2-hours)||POWER MANAGEMENT (1-hour)||ENHANCED SECURE DIGITAL HOST CONTROLLER (1-hour)||ETHERNET MACS (1-hour)||PARSER (WRIOP-CTLU) (1-hour)||SECURITY ENGINE (3-hours)||QUICC ENGINE - BUFFER MANAGEMENT (1-hour)|
|SYSTEM MMU, MMU500 (1-hour)||DDR4 CONTROLLER (2-hours)||SATA CONTROLLER (1-hour)||QUEUE BUFFER MANAGER (2-hours)||CTLU QOS MAPPING AND POLICER (2-hours)||PATTERN MATCH ENGINE (1-hour)||QUICC ENGINE - UNIFIED COMMUNICATION CONTROLLERS (1-hour)|
|HARDWARE IMPLEMENTATION (2-hours)||INTEGRATED FLASH CONTROLLER (2-hours)||QUEUE DIRECT MEMORY ACCESS (qDMA) (1-hour)||WIRE RATE IO PROCESSOR (2-hours)||MULTI FIELD LOOKUP UNIT (MFLU) (1-hour)||DECOMPRESSION AND COMPRESSION ENGINE (DCE) (1-hour)||QUICC ENGINE - UCC HDLC CONTROLLER (1-hour)|
|CLOCKING AND RESET (1-hour)||PCIE BRIDGE (1-hour)||USB3 CONTROLLERS (1-hour)||AIOP CLASSIFIER AND TABLE LOOKUP UNIT (1-hour)||QUICC ENGINE - UCC TRANSPARENT CONTROLLER (1-hour)|
|LOW SPEED SERIAL INTERFACES (1/2–hour)||MULTI-CHANNEL CONTROLLER ON UCC - UMCC (2-hours)|
|FLEXTIMER MODULE (1/2-hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A53: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
SoC Software Package (SSP) for the NXP LS1088A: implements drivers for interrupt controller, memory controllers, uart and edma. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set.