
Course Objectives
This course aims to explain the architecture of the NXP T1040 and T1042 SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.
General Information
Prerequisites
- Experience with a 32-bit processor or DSP is mandatory
- The e5500 CPU is covered by a separate course entitled NXP_E5500
Duration & Attendance
- From 5 to 8 days
- Min/max number of participants: 3-15
Location
Target Audience
Engineers and technicians who develop boards and software based on T1040/T1042.
Program Overview
Day 1 | Day 2 | Day 3 | Day 4 | Day 5 |
---|---|---|---|---|
OVERVIEW (1 hour) | HARDWARE IMPLEMENTATION (2 hours) | PCIE BRIDGE (2 hours) | USB CONTROLLERS (1 hour) | DPAA OVERVIEW (1 hour) |
INTERCONNECT (2 hours) | CLOCKING AND RESET (1 hour) | ENHANCED SECURE DIGITAL HOST CONTROLLER (2 hours) | PROGRAMMABLE INTERRUPT CONTROLLER (1 hour) | ETHERNET MACS (1 hour) |
PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU) (2 hours) | TRUST ARCHITECTURE (1 hour) | SATA HOST CONTROLLER (1 hour) | SECURITY ENGINE (3 hours) | QUEUE MANAGER (3 hours) |
CORENET PLATFORM CACHE (2 hours) | DDR4 CONTROLLER (2 hours) | DISPLAY INTERFACE UNIT (1 hour) | LOW SPEED SERIAL INTERFACES (1 hour) | BUFFER MANAGER (2 hours) |
INTEGRATED FLASH CONTROLLER (1 hour) | DMA CONTROLLER (1 hour) | PERFORMANCE MONITOR AND DEBUG FEATURES (1 hour) |
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Additional Information
Teaching Methods & Tools
Evaluation & Certification
Technical Material
Complementary Products & Services

CPU Software Package (CSP) for the e5500: implements exceptions, L1 and L2 cache and MMU paging
SoC Software Package (SSP) for the P1040: implements drivers for interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.