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NXP T1040

NXP T1040

Course Family:
NXP QorIQ T Series Processors
SKU/Ref:
NXP_T1040

Course Objectives

This course aims to explain the architecture of the NXP T1040 and T1042 SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • The e5500 CPU is covered by a separate course entitled NXP_E5500

Duration & Attendance

  • From 5 to 8 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on T1040/T1042.

Program Overview

Day 1 Day 2 Day 3 Day 4 Day 5
OVERVIEW (1 hour) HARDWARE IMPLEMENTATION (2 hours) PCIE BRIDGE (2 hours) USB CONTROLLERS (1 hour) DPAA OVERVIEW (1 hour)
INTERCONNECT (2 hours) CLOCKING AND RESET (1 hour) ENHANCED SECURE DIGITAL HOST CONTROLLER (2 hours) PROGRAMMABLE INTERRUPT CONTROLLER (1 hour) ETHERNET MACS (1 hour)
PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU) (2 hours) TRUST ARCHITECTURE (1 hour) SATA HOST CONTROLLER (1 hour) SECURITY ENGINE (3 hours) QUEUE MANAGER (3 hours)
CORENET PLATFORM CACHE (2 hours) DDR4 CONTROLLER (2 hours) DISPLAY INTERFACE UNIT (1 hour) LOW SPEED SERIAL INTERFACES (1 hour) BUFFER MANAGER (2 hours)
  INTEGRATED FLASH CONTROLLER (1 hour) DMA CONTROLLER (1 hour) PERFORMANCE MONITOR AND DEBUG FEATURES (1 hour)  

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the e5500: implements exceptions, L1 and L2 cache and MMU paging

SoC Software Package (SSP) for the P1040: implements drivers for interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.

Contact us to Learn More

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