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NXP P2020

NXP P2020

Course Family:
NXP QorlQ P series Processors
SKU/Ref:
NXP_P2020

Course Objectives

This course aims to explain the architecture of the NXP P2020 SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • The e500 CPU is covered by a separate course entitled NXP_E500

Duration & Attendance

  • 4 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on P2020.

Program Overview

Day 1 Day 2 Day 3 Day 4
OVERVIEW (1 hour) CLOCKING AND RESET (2 hours) SRIO BRIDGE (2 hours) SECURITY ENGINE (2 hours)
INTERCONNECT (2 hours) DDR3 CONTROLLER (2 hours) ENHANCED SECURE DIGITAL HOST CONTROLLER (2 hours) ENHANCED THREE SPEED ETHERNET CONTROLLERS (3 hours)
L2 CACHE (2 hours) ENHANCED LOCAL BUS CONTROLLER (2 hours) DMA CONTROLLER (1 hour) LOW SPEED SERIAL INTERFACES (1 hour)
HARDWARE IMPLEMENTATION (2 hours) PCIE BRIDGE (1 hour) USB CONTROLLER (1 hour) SOC PERFORMANCE MONITOR AND DEBUG FEATURES (1 hour)
    PROGRAMMABLE INTERRUPT CONTROLLER (1 hour)  

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the e500: implements exceptions, L1 cache and MMU paging

SoC Software Package (SSP) for the P2020: implements drivers for L2 cache, interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.

Optimized FFT: software implementation of a fixed point/floating point FFT using the SPE SIMD instruction set

Contact us to Learn More

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