This course aims to enable participants to design safety critical systems based on multi-core SoCs. After having defined the important multicore concepts, attendees will learn these concepts are implemented in both NXP SoCs. Benefits of platform virtualization are explained. Participants will study how the processor and the I/O MMUs can be used to implement separate spatial domains to ensure isolation between partitions.
- Experience with a 32-bit processor or DSP is mandatory
- See the courses on PowerPC QorIQ and ARM LayerScape SoCs.
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop safety-critical systems based on NXP multi-core SoCs, such as QorIQ, LayerScape, Qorivva and i.MX series.
|Day 1||Day 2||Day 3|
|INTRODUCTION TO MULTICORE CONCEPTS (3 hours)||CACHE COHERENCY (3 hours)||SPATIAL ISOLATION, PROCESSOR MMU (2 hours)|
|NXP MULTICORE PLATFORMS (1 hour)||SHARED RESOURCE MANAGEMENT (2 hours)||SPATIAL ISOLATION, IO MMU (2 hours)|
|VIRTUALIZATION (3 hours)||EXCEPTION MANAGEMENT (2 hours)||INTERCONNECT (2 hours)|
|DEBUGGING A MULTICORE SYSTEM (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.