This course aims to enable participants to design, verify or debug AXI-based IPs or interconnects. Participants get a detailed understanding of the AXI4, AXI4-ACE, AXI4-Stream and AXI4-lite protocols. In order to explain the purpose of particular AXI signals, an introduction to TrustZone, exclusive resource management and MPU/MMU page attributes is provided. The attendees will learn about AXI ordering rules, that are required to understand the operation of an interconnect. They will also study cache hardware coherency through AXI4-ACE protocol.
- Familiarity with Cortex ARM CPUs
- Knowledge of MMU and caches operation is recommended.
Duration & Attendance
- 2 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs or IPs based on ARM AMBA AXI buses.
|Day 1||Day 2|
|AXI 3 AND AXI 4 (4 hours)||INTRODUCTION TO CACHE AND TLB COHERENCY (1 hour)|
|AXI 4-Lite (1/2 hour)||AXI 4-ACE AND AXI 4-ACE LITE (4 hours)|
|AXI 4-Stream (1 hour)||CCI-500 CACHE COHERENT INTERCONNECT (2 hours)|
|LPD-500 LOW POWER DISTRIBUTOR (1/2 hour)|
|NIC-400 INTERCONNECT (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.