This course aims to explain the architecture of the ARM Cortex-A5 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the AArch32 V7-A specification. They will study the complex mechanisms specific to ARM V7-A processors, particularly TrustZone and MMU.
Duration & Attendance
- 5 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-A5 architecture.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|ARM BASICS||TRUSTZONE||L1 CACHES||GIC, TIMERS AND LOW POWER MODES||V7-A INSTRUCTION SET SUMMARY|
|CORTEX-A5 ARCHITECTURE||PAGE ATTRIBUTES||HARDWARE CACHE COHERENCY||CORESIGHT DEBUG||FLOATING-POINT UNIT|
|HARDWARE IMPLEMENTATION||MEMORY MANAGEMENT UNIT||PL310 L2 CACHE||PERFORMANCE MONITOR||EMBEDDED SOFTWARE DEVELOPMENT|
|INSTRUCTION PIPELINE||EXCLUSIVE RESOURCE MANAGEMENT|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A5: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode. This CSP is an ideal starting point for developing engineering test software, verification software, and proprietary RTOS or bare-metal applications. Engineering test software, verification software and proprietary RTOS or bare-metal applications can be developed from this CSP
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set