This course aims to explain the architecture of the ARM Cortex-R5 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the V7-R specification. They will study the mechanisms specific to ARM V7-R processors, particularly caches, TCMs and MPU. In addition to the CPU, the external IPs PL192 VIC and L2C-310 Level 2 cache are also explained. Labs contribute to become familiar with Cortex-R programming.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R6 architecture.
|Day 1||Day 2||Day 3||Day 4|
|ARM BASICS (2 hours)||EXCEPTION MECHANISM AND LOW POWER MODES (2 hours)||PL310 L2 CACHE (2 hours)||V7-R INSTRUCTION SET SUMMARY (3 hours)|
|CORTEX-R5 ARCHITECTURE (2 hours)||MEMORY PROTECTION UNIT (2 hours)||EXCLUSIVE RESOURCE MANAGEMENT (2 hours)||FLOATING-POINT UNIT (2 hours)|
|HARDWARE IMPLEMENTATION (1 hour)||CACHES AND TCMS (2 hours)||CORESIGHT DEBUG (3 hours)||EMBEDDED SOFTWARE DEVELOPMENT (3 hours)|
|INSTRUCTION PIPELINE (2 hours)||HARDWARE CACHE COHERENCY (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.