This course aims to explain the architecture of the NXP e500v2 PowerPC CPU to enable participants to efficiently develop low level software for MPC85XX and P1/P2 QorIQ SoCs. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the PowerPC Book E specification. They will study the complex mechanisms specific to PowerPC processors, particularly pipeline, cache and MMU.
Duration & Attendance
- 4 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software based on e500 CPU.
|Day 1||Day 2||Day 3||Day 4|
|OVERVIEW (1 hour)||MEMORY MANAGEMENT UNIT (4 hours)||HARDWARE CACHE COHERENCY (2 hours)||SCALAR FLOATING-POINT UNIT (2 hours)|
|INSTRUCTION PIPELINE (3 hours)||DATA AND INSTRUCTION PATHS (1 hour)||DEBUG (2 hours)||SIGNAL PROCESSING ENGINE (SPE) (5 hours)|
|EXCEPTION MECHANISM (3 hours)||L1 CACHES (2-hour)||CLOCKING AND POWER MANAGEMENT (1 hour)|
|ASSEMBLER PROGRAMMING (1 hour)|
|EABI (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e500: implements exceptions, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
Optimized FFT: software implementation of a fixed point/floating point FFT using the SPE SIMD instruction set