This course aims to explain the architecture of the NXP e600 PowerPC CPU to enable participants to efficiently develop low level software for MPC7448 and MPC86XX SoCs. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the PowerPC 32-bit specification. They will study the complex mechanisms specific to PowerPC processors, particularly pipeline, cache and MMU.
Duration & Attendance
- 5 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software based on e600 or MPC7448 CPU.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||MEMORY MANAGEMENT UNIT (4 hours)||L2 CACHE (2 hours)||HARDWARE IMPLEMENTATION (4 hours)||FLOATING-POINT UNIT (2 hours)|
|INSTRUCTION PIPELINE (3 hours)||DATA AND INSTRUCTION PATHS (1 hour)||HARDWARE CACHE COHERENCY (2 hours)||ASSEMBLER PROGRAMMING (2 hours)||VECTOR UNITS (ALTIVEC) (5 hours)|
|EXCEPTION MECHANISM (3 hours)||L1 CACHES (2 hours)||DEBUG (2 hours)||EABI (1 hour)|
|CLOCKING AND POWER MANAGEMENT (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e600: implements exceptions, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
Optimized FFT: software implementation of a fixed point/floating point FFT using the Altivec SIMD instruction set