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NXP i.MX8M

NXP i.MX8M

Course Family:
NXP i.MX Application Processors
SKU/Ref:
NXP_IMX8M

Course Objectives

This course aims to explain the architecture of the NXP i.MX8M SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, GPU, memory and peripherals. They will study the complex I/O peripherals including the multimedia units.

General Information

Prerequisites

  • Experience with a 32-bit processor or DSP is mandatory
  • Note that ARM CPUs are covered by separate courses, see ARM_A53 and ARM_M4

Duration & Attendance

  • 5 days
  • Min/max number of participants: 3-15

Location

On site/intra

Target Audience

Engineers and technicians who develop boards and software based on i.MX8M Dual/QuadLite/Quad.

Program Overview

Day 1 Day 2 Day 3 Day 4 Day 5
OVERVIEW (1-hour) SYSTEM RESET CONTROLLER (SRC) (2-hours) PCIE BRIDGE (1-hour) VIDEO UNITS (5-hour) SECURITY (6-hour)
INTERCONNECT (1-hour) BOOT PROCESS (2-hours) QUAD SPI (1-hour) AUDIO SUB-SYSTEM (2-hours) LOW SPEED INTERFACES (1-hour)
HARDWARE IMPLEMENTATION (2-hours) GENERAL POWER CONTROLLER (GPC) (1-hour) ENHANCED SECURE DIGITAL HOST CONTROLLER (1-hour)    
IOMUX (1-hour) DDR CONTROLLER (2-hours) GIGA ETHERNET MAC (1-hours)    
CLOCK CONTROLLER MODULE (CCM) (1-hour)   GENERAL PURPOSE MEDIA INTERFACE (GPMI) - upon request    
TIMERS (1-hour)   USB3.0 CONTROLLERS (1-hour)    
    SMART DMA (SDMA) (1-hour)    
    ENHANCED CONFIGURABLE SERIAL PERIPHERAL INTERFACE (eCSPI) (1-hour)    

 

The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.

Additional Information

Teaching Methods & Tools
Lectures with supporting slides, use of projector
Review and execution of bare-metal drivers, using GCC compiler and Lauterbach Trace32 debugger
Evaluation & Certification
Trainees are quizzed orally at the end of each chapter
Each trainee will fill out and return a training evaluation form upon completion of the training course
All attendees receive a Certificate of Completion upon completion of the training course
Technical Material
Training manuals given to attendees during training in pdf format
Attendees should bring their laptops for local access to course material (presentation, datasheets, …)
Notepad and pen are provided

Complementary Products & Services

CPU Software Package (CSP) for the ARM® Cortex™-A53: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and multicore in SMP or AMP mode

SoC Software Package (SSP) for the NXP i.MX8M: implements drivers for interrupt controller, SDMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications

Contact us to Learn More

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