This course aims to explain the architecture of the NXP MPC8641D SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.
- Experience with a 32-bit processor or DSP is mandatory
- The e600 CPU is covered by a separate course entitled NXP_E600
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on MPC8641D.
|Day 1||Day 2||Day 3|
|OVERVIEW (1 hour)||LOCAL BUS CONTROLLER (2 hours)||PROGRAMMABLE INTERRUPT CONTROLLER (2 hours)|
|INTERCONNECT (1 hour)||PCIE BRIDGE (2 hours)||ENHANCED THREE SPEED ETHERNET CONTROLLERS (3 hours)|
|HARDWARE IMPLEMENTATION (2 hours)||SRIO BRIDGE (2 hours)||LOW SPEED SERIAL INTERFACES (1 hour)|
|CLOCKING AND RESET (1 hour)||DMA CONTROLLER (1 hour)||SOC PERFORMANCE MONITOR AND DEBUG FEATURES (1 hour)|
|DDR2 CONTROLLER (2 hours)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e600: implements exceptions, L1 cache, L2 cache, MMU paging
SoC Software Package (SSP) for the MPC8641D: implements drivers for interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the Altivec SIMD instruction set