This course aims to explain the architecture of the NXP MPC8349E SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.
- Experience with a 32-bit processor or DSP is mandatory
- The e300 CPU is covered by a separate course entitled NXP_E300
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on MPC8349E.
|Day 1||Day 2||Day 3|
|OVERVIEW (1 hour)||LOCAL BUS CONTROLLER (2 hours)||THREE SPEED ETHERNET CONTROLLERS (2 hours)|
|INTERCONNECT (1 hour)||PCI BRIDGE (2 hours)||USB CONTROLLERS (2 hours)|
|HARDWARE IMPLEMENTATION (2 hours)||DMA CONTROLLER (1 hour)||SECURITY ENGINE (2 hours)|
|CLOCKING AND RESET (1 hour)||INTEGRATED PROGRAMMABLE INTERRUPT CONTROLLER (1 hour)||LOW SPEED SERIAL INTERFACES (1 hour)|
|DDR2 CONTROLLER (2 hours)||TIMERS (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e300: implements exceptions, L1 cache and MMU paging
SoC Software Package (SSP) for the MPC8349E: implements drivers for interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.