This course aims to explain the architecture of the NXP LS1021A SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the network acceleration units.
- Experience with a 32-bit processor or DSP is mandatory
- Note that the Cortex-A7 is covered by another course entitled ARM_A7
Duration & Attendance
- 5 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on LS1021A.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||DDR4 CONTROLLER (2 hours)||SATA CONTROLLER (1 hour)||LOW SPEED SERIAL INTERFACES (1 hour)||QUICC ENGINE - SYSTEM INTERFACE (1 hour)|
|INTERCONNECT (1 hour)||INTEGRATED FLASH CONTROLLER (1 hour)||ENHANCED DIRECT MEMORY ACCESS (eDMA) (1 hour)||INTEGRATED INTERCHIP SOUND (I2S) / SYNCHRONOUS AUDIO INTERFACE (SAI) (1 hour)||QUICC ENGINE - BUFFER MANAGEMENT (1 hour)|
|SYSTEM MMU, MMU400 (1 hour)||PCIE BRIDGE (2 hours)||QUEUE DIRECT MEMORY ACCESS (qDMA) (1 hour)||SONY/PHILIPS DIGITAL INTERFACE (SPDIF) (1 hour)||QUICC ENGINE - UNIFIED COMMUNICATION CONTROLLERS (1 hour)|
|HARDWARE IMPLEMENTATION (1 hour)||QUAD SPI (1 hour)||TWO-DIMENSIONAL ANIMATION AND COMPOSITING ENGINE (2D-ACE) (1 hour)||ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) (1 hour)||QUICC ENGINE - UCC HDLC CONTROLLER (1 hour)|
|CLOCKING AND RESET (1 hour)||ENHANCED SECURE DIGITAL HOST CONTROLLER (1 hour)||USB CONTROLLERS (1 hour)||FLEXTIMER MODULE (1 hour)||QUICC ENGINE - UCC TRANSPARENT CONTROLLER (1 hour)|
|TRUST ARCHITECTURE (1 hour)||FLEXCAN CONTROLLERS (1 hour)||SECURITY ENGINE (2 hours)||MULTI-CHANNEL CONTROLLER ON UCC - UMCC (2 hours)|
|RUN CONTROL AND POWER MANAGEMENT (1 hour)||ENHANCED THREE SPEED ETHERNET CONTROLLERS (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A7: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
SoC Software Package (SSP) for the NXP LS1021A: implements drivers for interrupt controller, memory controllers, uart. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set