This course aims to explain the architecture of the NXP LS1043A SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including network accelerators.
- Experience with a 32-bit processor or DSP is mandatory
- Note that the Cortex-A53 ARM CPU is covered by another course entitled ARM_A53
Duration & Attendance
- From 5 to 6 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on LS1043A
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||RUN CONTROL AND POWER MANAGEMENT (1 hour)||ENHANCED SECURE DIGITAL HOST CONTROLLER (1 hour)||DPAA OVERVIEW (2 hours)||FRAME MANAGER (4-hour)|
|INTERCONNECT (1 hour)||DDR4 CONTROLLER (2 hours)||SATA CONTROLLER (1 hour)||ETHERNET MACS (1 hour)||SECURITY ENGINE (3-hour)|
|SYSTEM MMU, MMU500 (1 hour)||INTEGRATED FLASH CONTROLLER (1 hour)||ENHANCED DIRECT MEMORY ACCESS (eDMA) (1 hour)||QUEUE MANAGER (3 hours)|
|HARDWARE IMPLEMENTATION (1 hour)||PCIE BRIDGE (2 hours)||QUEUE DIRECT MEMORY ACCESS (qDMA) (1 hour)||BUFFER MANAGER (1 hour)|
|CLOCKING AND RESET (2 hours)||QUAD SPI (1 hour)||USB CONTROLLERS (1 hour)|
|TRUST ARCHITECTURE (1 hour)||LOW SPEED SERIAL INTERFACES (1 hour)|
|FLEXTIMER MODULE (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the ARM® Cortex™-A53: implements exceptions, GIC, L1 cache, L2 cache, MMU paging and supports multicore in SMP or AMP mode.
SoC Software Package (SSP) for the NXP LS1043A: implements drivers for interrupt controller, memory controllers, uart and edma. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the NEON SIMD instruction set