This course aims to explain the architecture of the NXP P1010 SoC to enable participants to efficiently design a board and develop or adapt boot and I/O drivers. Attendees will get a detailed understanding of the internal architecture, especially the various paths between CPU, memory and peripherals. They will study the complex I/O peripherals including the communication controllers.
- Experience with a 32-bit processor or DSP is mandatory
- The e500 CPU is covered by a separate course entitled NXP_E500
Duration & Attendance
- 5 days
- Min/max number of participants: 3-15
Engineers and technicians who develop boards and software based on P1010.
|Day 1||Day 2||Day 3||Day 4||Day 5|
|OVERVIEW (1 hour)||CLOCKING AND RESET (2 hours)||PCIE BRIDGE (2 hours)||SECURITY ENGINE (3 hours)||TDM INTERFACE (2 hours)|
|INTERCONNECT (2 hours)||TRUST ARCHITECTURE (1 hour)||ENHANCED SECURE DIGITAL HOST CONTROLLER (2 hours)||ENHANCED THREE SPEED ETHERNET CONTROLLERS (4 hours)||USB CONTROLLER (2 hours)|
|L2 CACHE (2 hours)||DDR3 CONTROLLER (2 hours)||DMA CONTROLLER (1 hour)||FLEXCAN MODULES (1 hour)|
|HARDWARE IMPLEMENTATION (2 hours)||INTEGRATED FLASH CONTROLLER (2 hours)||PROGRAMMABLE INTERRUPT CONTROLLER (2 hours)||LOW SPEED SERIAL INTERFACES (1 hour)|
|SOC PERFORMANCE MONITOR AND DEBUG FEATURES (1 hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.
Teaching Methods & Tools
Evaluation & Certification
Complementary Products & Services
CPU Software Package (CSP) for the e500: implements exceptions, L1 cache and MMU paging
SoC Software Package (SSP) for the P1010: implements drivers for L2 cache, interrupt controller, DMA, memory controllers, Ethernet. This CSP/SSP is an ideal starting point for developing proprietary RTOS or bare-metal applications.
Optimized FFT: software implementation of a fixed point/floating point FFT using the SPE SIMD instruction set