This course aims to explain the architecture of the C66x TI DSP to enable participants to efficiently design software. Attendees will get a detailed understanding of the internal architecture, especially the instruction pipeline. They will study how to design efficient C/assembler programs.
- Experience with a 32-bit processor or DSP is mandatory
- The Keystone I is covered by another course entitled TI_KS1C6672
Duration & Attendance
- 3 days
- Min/max number of participants: 3-15
Engineers and technicians who develop software for C66x DSP cores.
|Day 1||Day 2||Day 3|
|OVERVIEW (1 hour)||CODE COMPOSER STUDIO IDE (2 hours)||ASSEMBLER BASICS (1-hour)|
|CPU DATA PATHS AND CONTROL (2 hours)||EXCEPTION MANAGAMENT (2 hours)||INTRODUCTION TO ASSEMBLER PROGRAMMING (1-hour)|
|INSTRUCTION PIPELINE (2 hours)||CACHES (2 hours)||ADDRESSING MODES (1-hour)|
|SOFTWARE PIPELINED LOOPS (2 hours)||INTERFACE TO SOC INTERCONNECT (1 hour)||BRANCH INSTRUCTIONS (1-hour)|
|LOGICAL INSTRUCTIONS (1-hour)|
|ARITHMETIC SCALAR INSTRUCTIONS (1-hour)|
|ARITHMETIC VECTOR INSTRUCTIONS (1-hour)|
The detailed course program is available upon request. For on-site training, we can provide a customized program specifically tailored for your audience, needs, and schedule. Contact us to discuss this option.